Espressif Systems /ESP32-H2 /SOC_ETM /CH_ENA_AD0_SET

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as CH_ENA_AD0_SET

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CH_SET0)CH_SET0 0 (CH_SET1)CH_SET1 0 (CH_SET2)CH_SET2 0 (CH_SET3)CH_SET3 0 (CH_SET4)CH_SET4 0 (CH_SET5)CH_SET5 0 (CH_SET6)CH_SET6 0 (CH_SET7)CH_SET7 0 (CH_SET8)CH_SET8 0 (CH_SET9)CH_SET9 0 (CH_SET10)CH_SET10 0 (CH_SET11)CH_SET11 0 (CH_SET12)CH_SET12 0 (CH_SET13)CH_SET13 0 (CH_SET14)CH_SET14 0 (CH_SET15)CH_SET15 0 (CH_SET16)CH_SET16 0 (CH_SET17)CH_SET17 0 (CH_SET18)CH_SET18 0 (CH_SET19)CH_SET19 0 (CH_SET20)CH_SET20 0 (CH_SET21)CH_SET21 0 (CH_SET22)CH_SET22 0 (CH_SET23)CH_SET23 0 (CH_SET24)CH_SET24 0 (CH_SET25)CH_SET25 0 (CH_SET26)CH_SET26 0 (CH_SET27)CH_SET27 0 (CH_SET28)CH_SET28 0 (CH_SET29)CH_SET29 0 (CH_SET30)CH_SET30 0 (CH_SET31)CH_SET31

Description

channel enable set register

Fields

CH_SET0

ch0 set

CH_SET1

ch1 set

CH_SET2

ch2 set

CH_SET3

ch3 set

CH_SET4

ch4 set

CH_SET5

ch5 set

CH_SET6

ch6 set

CH_SET7

ch7 set

CH_SET8

ch8 set

CH_SET9

ch9 set

CH_SET10

ch10 set

CH_SET11

ch11 set

CH_SET12

ch12 set

CH_SET13

ch13 set

CH_SET14

ch14 set

CH_SET15

ch15 set

CH_SET16

ch16 set

CH_SET17

ch17 set

CH_SET18

ch18 set

CH_SET19

ch19 set

CH_SET20

ch20 set

CH_SET21

ch21 set

CH_SET22

ch22 set

CH_SET23

ch23 set

CH_SET24

ch24 set

CH_SET25

ch25 set

CH_SET26

ch26 set

CH_SET27

ch27 set

CH_SET28

ch28 set

CH_SET29

ch29 set

CH_SET30

ch30 set

CH_SET31

ch31 set

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