channel enable set register
CH_SET0 | ch0 set |
CH_SET1 | ch1 set |
CH_SET2 | ch2 set |
CH_SET3 | ch3 set |
CH_SET4 | ch4 set |
CH_SET5 | ch5 set |
CH_SET6 | ch6 set |
CH_SET7 | ch7 set |
CH_SET8 | ch8 set |
CH_SET9 | ch9 set |
CH_SET10 | ch10 set |
CH_SET11 | ch11 set |
CH_SET12 | ch12 set |
CH_SET13 | ch13 set |
CH_SET14 | ch14 set |
CH_SET15 | ch15 set |
CH_SET16 | ch16 set |
CH_SET17 | ch17 set |
CH_SET18 | ch18 set |
CH_SET19 | ch19 set |
CH_SET20 | ch20 set |
CH_SET21 | ch21 set |
CH_SET22 | ch22 set |
CH_SET23 | ch23 set |
CH_SET24 | ch24 set |
CH_SET25 | ch25 set |
CH_SET26 | ch26 set |
CH_SET27 | ch27 set |
CH_SET28 | ch28 set |
CH_SET29 | ch29 set |
CH_SET30 | ch30 set |
CH_SET31 | ch31 set |